=== CPU Information ===
Architecture:                         x86_64
CPU op-mode(s):                       32-bit, 64-bit
Address sizes:                        48 bits physical, 48 bits virtual
Byte Order:                           Little Endian
CPU(s):                               32
On-line CPU(s) list:                  0-31
Vendor ID:                            AuthenticAMD
Model name:                           AMD Ryzen 9 5950X 16-Core Processor
CPU family:                           25
Model:                                33
Thread(s) per core:                   2
Core(s) per socket:                   16
Socket(s):                            1
Stepping:                             2
Frequency boost:                      enabled
CPU(s) scaling MHz:                   20%
CPU max MHz:                          5084.0000
CPU min MHz:                          550.0000
BogoMIPS:                             6786.92
Flags:                                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local user_shstk clzero irperf xsaveerptr rdpru wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm debug_swap
Virtualization:                       AMD-V
L1d cache:                            512 KiB (16 instances)
L1i cache:                            512 KiB (16 instances)
L2 cache:                             8 MiB (16 instances)
L3 cache:                             64 MiB (2 instances)
NUMA node(s):                         1
NUMA node0 CPU(s):                    0-31
Vulnerability Gather data sampling:   Not affected
Vulnerability Itlb multihit:          Not affected
Vulnerability L1tf:                   Not affected
Vulnerability Mds:                    Not affected
Vulnerability Meltdown:               Not affected
Vulnerability Mmio stale data:        Not affected
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed:               Not affected
Vulnerability Spec rstack overflow:   Mitigation; Safe RET
Vulnerability Spec store bypass:      Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2:             Mitigation; Retpolines; IBPB conditional; IBRS_FW; STIBP always-on; RSB filling; PBRSB-eIBRS Not affected; BHI Not affected
Vulnerability Srbds:                  Not affected
Vulnerability Tsx async abort:        Not affected
lscpu: options --all, --online and --offline may only be used with options --extended or --parse.
NAME ONE-SIZE ALL-SIZE WAYS TYPE        LEVEL  SETS PHY-LINE COHERENCY-SIZE
L1d       32K     512K    8 Data            1    64        1             64
L1i       32K     512K    8 Instruction     1    64        1             64
L2       512K       8M    8 Unified         2  1024        1             64
L3        32M      64M   16 Unified         3 32768        1             64
CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE    MAXMHZ   MINMHZ       MHZ
  0    0      0    0 0:0:0:0          yes 5084.0000 550.0000  550.0000
  1    0      0    1 1:1:1:0          yes 5084.0000 550.0000 5034.0151
  2    0      0    2 2:2:2:0          yes 5084.0000 550.0000  550.0000
  3    0      0    3 3:3:3:0          yes 5084.0000 550.0000  550.0000
  4    0      0    4 4:4:4:0          yes 5084.0000 550.0000  550.0000
  5    0      0    5 5:5:5:0          yes 5084.0000 550.0000  550.0000
  6    0      0    6 6:6:6:0          yes 5084.0000 550.0000  550.0000
  7    0      0    7 7:7:7:0          yes 5084.0000 550.0000  550.0000
  8    0      0    8 8:8:8:1          yes 5084.0000 550.0000  550.0000
  9    0      0    9 9:9:9:1          yes 5084.0000 550.0000  550.0000
 10    0      0   10 10:10:10:1       yes 5084.0000 550.0000  550.0000
 11    0      0   11 11:11:11:1       yes 5084.0000 550.0000  550.0000
 12    0      0   12 12:12:12:1       yes 5084.0000 550.0000  550.0000
 13    0      0   13 13:13:13:1       yes 5084.0000 550.0000  550.0000
 14    0      0   14 14:14:14:1       yes 5084.0000 550.0000  550.0000
 15    0      0   15 15:15:15:1       yes 5084.0000 550.0000  550.0000
 16    0      0    0 0:0:0:0          yes 5084.0000 550.0000 4013.0149
 17    0      0    1 1:1:1:0          yes 5084.0000 550.0000  550.0000
 18    0      0    2 2:2:2:0          yes 5084.0000 550.0000 4029.5701
 19    0      0    3 3:3:3:0          yes 5084.0000 550.0000  550.0000
 20    0      0    4 4:4:4:0          yes 5084.0000 550.0000  550.0000
 21    0      0    5 5:5:5:0          yes 5084.0000 550.0000  550.0000
 22    0      0    6 6:6:6:0          yes 5084.0000 550.0000  550.0000
 23    0      0    7 7:7:7:0          yes 5084.0000 550.0000  550.0000
 24    0      0    8 8:8:8:1          yes 5084.0000 550.0000  550.0000
 25    0      0    9 9:9:9:1          yes 5084.0000 550.0000  550.0000
 26    0      0   10 10:10:10:1       yes 5084.0000 550.0000  550.0000
 27    0      0   11 11:11:11:1       yes 5084.0000 550.0000 3586.3059
 28    0      0   12 12:12:12:1       yes 5084.0000 550.0000 3591.6411
 29    0      0   13 13:13:13:1       yes 5084.0000 550.0000  550.0000
 30    0      0   14 14:14:14:1       yes 5084.0000 550.0000  550.0000
 31    0      0   15 15:15:15:1       yes 5084.0000 550.0000  550.0000
=== RAM Information ===
               total        used        free      shared  buff/cache   available
Mem:           125Gi       1.1Gi       125Gi       1.1Mi       123Mi       124Gi
Swap:             0B          0B          0B
=== CPU Topology ===
Machine (126GB total)
  Package L#0
    NUMANode L#0 (P#0 126GB)
    L3 L#0 (32MB)
      L2 L#0 (512KB) + L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0
        PU L#0 (P#0)
        PU L#1 (P#16)
      L2 L#1 (512KB) + L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1
        PU L#2 (P#1)
        PU L#3 (P#17)
      L2 L#2 (512KB) + L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2
        PU L#4 (P#2)
        PU L#5 (P#18)
      L2 L#3 (512KB) + L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3
        PU L#6 (P#3)
        PU L#7 (P#19)
      L2 L#4 (512KB) + L1d L#4 (32KB) + L1i L#4 (32KB) + Core L#4
        PU L#8 (P#4)
        PU L#9 (P#20)
      L2 L#5 (512KB) + L1d L#5 (32KB) + L1i L#5 (32KB) + Core L#5
        PU L#10 (P#5)
        PU L#11 (P#21)
      L2 L#6 (512KB) + L1d L#6 (32KB) + L1i L#6 (32KB) + Core L#6
        PU L#12 (P#6)
        PU L#13 (P#22)
      L2 L#7 (512KB) + L1d L#7 (32KB) + L1i L#7 (32KB) + Core L#7
        PU L#14 (P#7)
        PU L#15 (P#23)
    L3 L#1 (32MB)
      L2 L#8 (512KB) + L1d L#8 (32KB) + L1i L#8 (32KB) + Core L#8
        PU L#16 (P#8)
        PU L#17 (P#24)
      L2 L#9 (512KB) + L1d L#9 (32KB) + L1i L#9 (32KB) + Core L#9
        PU L#18 (P#9)
        PU L#19 (P#25)
      L2 L#10 (512KB) + L1d L#10 (32KB) + L1i L#10 (32KB) + Core L#10
        PU L#20 (P#10)
        PU L#21 (P#26)
      L2 L#11 (512KB) + L1d L#11 (32KB) + L1i L#11 (32KB) + Core L#11
        PU L#22 (P#11)
        PU L#23 (P#27)
      L2 L#12 (512KB) + L1d L#12 (32KB) + L1i L#12 (32KB) + Core L#12
        PU L#24 (P#12)
        PU L#25 (P#28)
      L2 L#13 (512KB) + L1d L#13 (32KB) + L1i L#13 (32KB) + Core L#13
        PU L#26 (P#13)
        PU L#27 (P#29)
      L2 L#14 (512KB) + L1d L#14 (32KB) + L1i L#14 (32KB) + Core L#14
        PU L#28 (P#14)
        PU L#29 (P#30)
      L2 L#15 (512KB) + L1d L#15 (32KB) + L1i L#15 (32KB) + Core L#15
        PU L#30 (P#15)
        PU L#31 (P#31)
  HostBridge
    PCIBridge
      PCI 01:00.0 (NVMExp)
        Block(Disk) "nvme0n1"
    PCIBridge
      PCI 02:00.1 (SATA)
        Block(Disk) "sda"
      PCIBridge
        PCIBridge
          PCI 05:00.0 (Ethernet)
            Net "enp5s0"
    PCIBridge
      PCIBridge
        PCIBridge
          PCI 08:00.0 (VGA)
  Misc(MemoryModule)
  Misc(MemoryModule)
  Misc(MemoryModule)
  Misc(MemoryModule)
=== Kernel Version ===
6.12.27-amd64
=== Scheduler Settings (/proc/sys/kernel/sched*) ===
sched_autogroup_enabled: 1
sched_cfs_bandwidth_slice_us: 5000
sched_deadline_period_max_us: 4194304
sched_deadline_period_min_us: 100
sched_energy_aware: 
sched_itmt_enabled: 1
sched_rr_timeslice_ms: 100
sched_rt_period_us: 1000000
sched_rt_runtime_us: 950000
sched_schedstats: 0
